URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] - Rev 20

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Rev	Log message	Author	Age	Path
20	added Nexys2 support expanded docs created tools directory	jt_eaton	5215d 13h	/socgen/
19	added serial_xmit module updated and added docs	jt_eaton	5222d 19h	/socgen/
18	added geda support files and docs	jt_eaton	5227d 18h	/socgen/
17	removed old doc files	jt_eaton	5229d 19h	/socgen/
16	added geda scripts and symbols/sch	jt_eaton	5229d 19h	/socgen/
15	added io_module with ps2 and uart added soc_mouse with uart and mouse interface fixed latch in mrisc	jt_eaton	5235d 22h	/socgen/
14	add web_uploads	jt_eaton	5246d 02h	/socgen/
13	updated for xilinx webpack 11.1	jt_eaton	5253d 16h	/socgen/
12	switched Makefile to use xilinx 11.1 ise removed timescale from synthesis files now use consist timescale header in all sims	jt_eaton	5254d 03h	/socgen/
11	moved bsdl files renamed ucf file	jt_eaton	5259d 22h	/socgen/
10	added impact_bat to generate svf files	jt_eaton	5260d 00h	/socgen/
9	updated build_cmp and cleaned up fpga script added more utility tools	jt_eaton	5262d 01h	/socgen/
8	fixed loop sim, now pick up ROM_WORDS from sw dir	jt_eaton	5264d 00h	/socgen/
7	changed loop to use subroutines fixed typo on variants name	jt_eaton	5265d 00h	/socgen/
6	added pic_micro from minirisc project with design to run code on a digilent Basys board	jt_eaton	5268d 20h	/socgen/
5	added testbench and generic clock model	jt_eaton	5270d 01h	/socgen/
4	added generic model for single ended generic pad	jt_eaton	5270d 02h	/socgen/
3	started bin and lib directories, added install instructions for ubuntu 9.04	jt_eaton	5270d 15h	/socgen/
2	added starting docs	jt_eaton	5271d 23h	/socgen/
1	The project and the structure was created	root	5272d 11h	/socgen/

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Subversion Repositories socgen

[/] [socgen/] - Rev 20

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