URL https://opencores.org/ocsvn/socgen/socgen/trunk

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[/] [socgen/] - Rev 51

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Rev	Log message	Author	Age	Path
51	removed old test	jt_eaton	5051d 06h	/socgen/
50	clean up from last checkin	jt_eaton	5051d 06h	/socgen/
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5051d 09h	/socgen/
48	added support for covered code checking	jt_eaton	5073d 15h	/socgen/
47	removed old variant	jt_eaton	5087d 18h	/socgen/
46	removed hard coded component names from design files define file is always defines.v top level is always top.v	jt_eaton	5087d 18h	/socgen/
45	added 6502 sims/software and synth	jt_eaton	5094d 14h	/socgen/
44	added new parts and sw for 6502	jt_eaton	5094d 17h	/socgen/
43	complete rework of states and sequencer added interrupts moved prog space and vectors to F space	jt_eaton	5104d 15h	/socgen/
42	removed old versions that used prog as C space	jt_eaton	5104d 16h	/socgen/
41	added kim-1 design and program now support Nexys2 sdram	jt_eaton	5122d 16h	/socgen/
40	removed test for deleted block	jt_eaton	5122d 17h	/socgen/
39	added io_probe to sims added boot rom into 6502 added T6502_control	jt_eaton	5131d 05h	/socgen/
38	fsm level removed	jt_eaton	5131d 05h	/socgen/
37	continued to clean up inst decodes to alu and move datapath out of sequencer removed latched alu_result, now uses raw	jt_eaton	5140d 12h	/socgen/
36	split out alu_ctrl block split out alu decode signals	jt_eaton	5141d 06h	/socgen/
35	added T6502 doc	jt_eaton	5142d 10h	/socgen/
34	removed BCD mode from T6502 started to convert design to use datapath logic for alu	jt_eaton	5147d 12h	/socgen/
33	removed unused block	jt_eaton	5147d 13h	/socgen/
32	renamed to T6502_state_fsm	jt_eaton	5147d 19h	/socgen/

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[/] [socgen/] - Rev 51

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