URL https://opencores.org/ocsvn/socgen/socgen/trunk

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[/] [socgen/] - Rev 56

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Rev	Log message	Author	Age	Path
56	soc_builder now builds verilog from xml files	jt_eaton	5045d 13h	/socgen/
55	removed pre-rout and gates sims	jt_eaton	5048d 10h	/socgen/
54	now set up fpga targets from xml files	jt_eaton	5048d 11h	/socgen/
53	fixed check_fpgas	jt_eaton	5051d 00h	/socgen/
52	removed noworking sims and syn	jt_eaton	5051d 01h	/socgen/
51	removed old test	jt_eaton	5051d 01h	/socgen/
50	clean up from last checkin	jt_eaton	5051d 01h	/socgen/
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5051d 04h	/socgen/
48	added support for covered code checking	jt_eaton	5073d 10h	/socgen/
47	removed old variant	jt_eaton	5087d 13h	/socgen/
46	removed hard coded component names from design files define file is always defines.v top level is always top.v	jt_eaton	5087d 13h	/socgen/
45	added 6502 sims/software and synth	jt_eaton	5094d 10h	/socgen/
44	added new parts and sw for 6502	jt_eaton	5094d 12h	/socgen/
43	complete rework of states and sequencer added interrupts moved prog space and vectors to F space	jt_eaton	5104d 11h	/socgen/
42	removed old versions that used prog as C space	jt_eaton	5104d 11h	/socgen/
41	added kim-1 design and program now support Nexys2 sdram	jt_eaton	5122d 12h	/socgen/
40	removed test for deleted block	jt_eaton	5122d 12h	/socgen/
39	added io_probe to sims added boot rom into 6502 added T6502_control	jt_eaton	5131d 00h	/socgen/
38	fsm level removed	jt_eaton	5131d 00h	/socgen/
37	continued to clean up inst decodes to alu and move datapath out of sequencer removed latched alu_result, now uses raw	jt_eaton	5140d 08h	/socgen/

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Subversion Repositories socgen

[/] [socgen/] - Rev 56

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