URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] - Rev 59

Rev	Log message	Author	Age	Path
59	added filelist.core to syn dirs to customize core	jt_eaton	5135d 21h	/socgen/
58	removed old Makefiles	jt_eaton	5136d 12h	/socgen/
57	Now generate all filelists from xml files	jt_eaton	5136d 12h	/socgen/
56	soc_builder now builds verilog from xml files	jt_eaton	5141d 21h	/socgen/
55	removed pre-rout and gates sims	jt_eaton	5144d 17h	/socgen/
54	now set up fpga targets from xml files	jt_eaton	5144d 18h	/socgen/
53	fixed check_fpgas	jt_eaton	5147d 07h	/socgen/
52	removed noworking sims and syn	jt_eaton	5147d 08h	/socgen/
51	removed old test	jt_eaton	5147d 08h	/socgen/
50	clean up from last checkin	jt_eaton	5147d 09h	/socgen/
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5147d 12h	/socgen/
48	added support for covered code checking	jt_eaton	5169d 18h	/socgen/
47	removed old variant	jt_eaton	5183d 21h	/socgen/
46	removed hard coded component names from design files define file is always defines.v top level is always top.v	jt_eaton	5183d 21h	/socgen/
45	added 6502 sims/software and synth	jt_eaton	5190d 17h	/socgen/
44	added new parts and sw for 6502	jt_eaton	5190d 20h	/socgen/
43	complete rework of states and sequencer added interrupts moved prog space and vectors to F space	jt_eaton	5200d 18h	/socgen/
42	removed old versions that used prog as C space	jt_eaton	5200d 18h	/socgen/
41	added kim-1 design and program now support Nexys2 sdram	jt_eaton	5218d 19h	/socgen/
40	removed test for deleted block	jt_eaton	5218d 19h	/socgen/