URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] - Rev 61

Rev	Log message	Author	Age	Path
61	now generate dut files for coverage removed use of lndir	jt_eaton	5039d 10h	/socgen/
60	moved alu_logic into seperate component	jt_eaton	5039d 21h	/socgen/
59	added filelist.core to syn dirs to customize core	jt_eaton	5039d 21h	/socgen/
58	removed old Makefiles	jt_eaton	5040d 12h	/socgen/
57	Now generate all filelists from xml files	jt_eaton	5040d 13h	/socgen/
56	soc_builder now builds verilog from xml files	jt_eaton	5045d 21h	/socgen/
55	removed pre-rout and gates sims	jt_eaton	5048d 18h	/socgen/
54	now set up fpga targets from xml files	jt_eaton	5048d 19h	/socgen/
53	fixed check_fpgas	jt_eaton	5051d 08h	/socgen/
52	removed noworking sims and syn	jt_eaton	5051d 09h	/socgen/
51	removed old test	jt_eaton	5051d 09h	/socgen/
50	clean up from last checkin	jt_eaton	5051d 09h	/socgen/
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5051d 12h	/socgen/
48	added support for covered code checking	jt_eaton	5073d 18h	/socgen/
47	removed old variant	jt_eaton	5087d 21h	/socgen/
46	removed hard coded component names from design files define file is always defines.v top level is always top.v	jt_eaton	5087d 21h	/socgen/
45	added 6502 sims/software and synth	jt_eaton	5094d 18h	/socgen/
44	added new parts and sw for 6502	jt_eaton	5094d 20h	/socgen/
43	complete rework of states and sequencer added interrupts moved prog space and vectors to F space	jt_eaton	5104d 19h	/socgen/
42	removed old versions that used prog as C space	jt_eaton	5104d 19h	/socgen/