URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] - Rev 70

Rev	Log message	Author	Age	Path
70	ignore work	jt_eaton	5055d 14h	/socgen/
69	added work dir	jt_eaton	5055d 14h	/socgen/
68	moved to seperate components	jt_eaton	5058d 14h	/socgen/
67	updated installs	jt_eaton	5058d 14h	/socgen/
66	converted sims to use parameters added msp and 6502 software installs	jt_eaton	5059d 14h	/socgen/
65	added params.sim to sims updated install's	jt_eaton	5064d 14h	/socgen/
64	added support for Fedora 13	jt_eaton	5068d 13h	/socgen/
63	added install config for Ubuntu 10.10	jt_eaton	5068d 20h	/socgen/
62	fixed parameters from `defines	jt_eaton	5072d 12h	/socgen/
61	now generate dut files for coverage removed use of lndir	jt_eaton	5072d 13h	/socgen/
60	moved alu_logic into seperate component	jt_eaton	5073d 00h	/socgen/
59	added filelist.core to syn dirs to customize core	jt_eaton	5073d 01h	/socgen/
58	removed old Makefiles	jt_eaton	5073d 16h	/socgen/
57	Now generate all filelists from xml files	jt_eaton	5073d 16h	/socgen/
56	soc_builder now builds verilog from xml files	jt_eaton	5079d 01h	/socgen/
55	removed pre-rout and gates sims	jt_eaton	5081d 21h	/socgen/
54	now set up fpga targets from xml files	jt_eaton	5081d 22h	/socgen/
53	fixed check_fpgas	jt_eaton	5084d 11h	/socgen/
52	removed noworking sims and syn	jt_eaton	5084d 12h	/socgen/
51	removed old test	jt_eaton	5084d 12h	/socgen/