URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] - Rev 83

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Rev	Log message	Author	Age	Path
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	4947d 17h	/socgen/
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	4962d 11h	/socgen/
81	morphing xml files to use 1685 removed log directories	jt_eaton	4983d 18h	/socgen/
80	now generate all sims and syns param and filelists for xml	jt_eaton	5013d 09h	/socgen/
79	removed unsupported code	jt_eaton	5019d 13h	/socgen/
78	removed unsupported fpga	jt_eaton	5019d 13h	/socgen/
77	now generate syn and cov Makefiles leave log and out files in sim/run directory	jt_eaton	5019d 14h	/socgen/
76	added wave.save files now generate sims Makefile and params.sim leave sim log and vcd files in sim/run/directory	jt_eaton	5021d 19h	/socgen/
75	added linting using verilator	jt_eaton	5025d 11h	/socgen/
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	5030d 17h	/socgen/
73	removed dup png files	jt_eaton	5038d 16h	/socgen/
72	split T6502 into components moved io_module into seperate project removed liblists direct loads filelists for sims and coverage add hier type into xml files to generate verilog	jt_eaton	5038d 19h	/socgen/
71	ignore anything in work	jt_eaton	5045d 11h	/socgen/
70	ignore work	jt_eaton	5045d 11h	/socgen/
69	added work dir	jt_eaton	5045d 11h	/socgen/
68	moved to seperate components	jt_eaton	5048d 11h	/socgen/
67	updated installs	jt_eaton	5048d 11h	/socgen/
66	converted sims to use parameters added msp and 6502 software installs	jt_eaton	5049d 10h	/socgen/
65	added params.sim to sims updated install's	jt_eaton	5054d 11h	/socgen/
64	added support for Fedora 13	jt_eaton	5058d 10h	/socgen/

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Subversion Repositories socgen

[/] [socgen/] - Rev 83

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