URL https://opencores.org/ocsvn/socgen/socgen/trunk

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[/] [socgen/] - Rev 87

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Rev	Log message	Author	Age	Path
87	removed prebuilt geda schematics and symbols	jt_eaton	4891d 21h	/socgen/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4899d 18h	/socgen/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4906d 17h	/socgen/
84	removed unneeded files	jt_eaton	4956d 22h	/socgen/
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	4957d 02h	/socgen/
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	4971d 20h	/socgen/
81	morphing xml files to use 1685 removed log directories	jt_eaton	4993d 03h	/socgen/
80	now generate all sims and syns param and filelists for xml	jt_eaton	5022d 18h	/socgen/
79	removed unsupported code	jt_eaton	5028d 22h	/socgen/
78	removed unsupported fpga	jt_eaton	5028d 22h	/socgen/
77	now generate syn and cov Makefiles leave log and out files in sim/run directory	jt_eaton	5028d 23h	/socgen/
76	added wave.save files now generate sims Makefile and params.sim leave sim log and vcd files in sim/run/directory	jt_eaton	5031d 04h	/socgen/
75	added linting using verilator	jt_eaton	5034d 20h	/socgen/
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	5040d 02h	/socgen/
73	removed dup png files	jt_eaton	5048d 02h	/socgen/
72	split T6502 into components moved io_module into seperate project removed liblists direct loads filelists for sims and coverage add hier type into xml files to generate verilog	jt_eaton	5048d 04h	/socgen/
71	ignore anything in work	jt_eaton	5054d 20h	/socgen/
70	ignore work	jt_eaton	5054d 20h	/socgen/
69	added work dir	jt_eaton	5054d 20h	/socgen/
68	moved to seperate components	jt_eaton	5057d 20h	/socgen/

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[/] [socgen/] - Rev 87

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