URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] - Rev 97

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Rev	Log message	Author	Age	Path
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4687d 01h	/socgen/
96	hierConnections now create ports	jt_eaton	4760d 22h	/socgen/
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4769d 19h	/socgen/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4796d 21h	/socgen/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4809d 09h	/socgen/
92	all testbenchs now built from /sim/xml files bench /models now in Testbench	jt_eaton	4814d 10h	/socgen/
91	fixed all sims, coverage not working	jt_eaton	4822d 04h	/socgen/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4822d 21h	/socgen/
89	removed unneeded debug directories	jt_eaton	4844d 05h	/socgen/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4844d 05h	/socgen/
87	removed prebuilt geda schematics and symbols	jt_eaton	4854d 22h	/socgen/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4862d 19h	/socgen/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4869d 18h	/socgen/
84	removed unneeded files	jt_eaton	4919d 23h	/socgen/
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	4920d 03h	/socgen/
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	4934d 21h	/socgen/
81	morphing xml files to use 1685 removed log directories	jt_eaton	4956d 04h	/socgen/
80	now generate all sims and syns param and filelists for xml	jt_eaton	4985d 19h	/socgen/
79	removed unsupported code	jt_eaton	4991d 23h	/socgen/
78	removed unsupported fpga	jt_eaton	4991d 23h	/socgen/

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Subversion Repositories socgen

[/] [socgen/] - Rev 97

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