URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] - Rev 98

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Rev	Log message	Author	Age	Path
98	removed unneeded sim	jt_eaton	4786d 13h	/socgen/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4786d 14h	/socgen/
96	hierConnections now create ports	jt_eaton	4860d 10h	/socgen/
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4869d 08h	/socgen/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4896d 09h	/socgen/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4908d 22h	/socgen/
92	all testbenchs now built from /sim/xml files bench /models now in Testbench	jt_eaton	4913d 23h	/socgen/
91	fixed all sims, coverage not working	jt_eaton	4921d 17h	/socgen/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4922d 09h	/socgen/
89	removed unneeded debug directories	jt_eaton	4943d 18h	/socgen/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4943d 18h	/socgen/
87	removed prebuilt geda schematics and symbols	jt_eaton	4954d 11h	/socgen/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4962d 08h	/socgen/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4969d 07h	/socgen/
84	removed unneeded files	jt_eaton	5019d 12h	/socgen/
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	5019d 16h	/socgen/
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	5034d 10h	/socgen/
81	morphing xml files to use 1685 removed log directories	jt_eaton	5055d 16h	/socgen/
80	now generate all sims and syns param and filelists for xml	jt_eaton	5085d 08h	/socgen/
79	removed unsupported code	jt_eaton	5091d 12h	/socgen/

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Subversion Repositories socgen

[/] [socgen/] - Rev 98

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