URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] - Rev 16

Rev	Log message	Author	Age	Path
16	added geda scripts and symbols/sch	jt_eaton	5241d 00h	/socgen/trunk/
15	added io_module with ps2 and uart added soc_mouse with uart and mouse interface fixed latch in mrisc	jt_eaton	5247d 03h	/socgen/trunk/
13	updated for xilinx webpack 11.1	jt_eaton	5264d 21h	/socgen/trunk/
12	switched Makefile to use xilinx 11.1 ise removed timescale from synthesis files now use consist timescale header in all sims	jt_eaton	5265d 08h	/socgen/trunk/
11	moved bsdl files renamed ucf file	jt_eaton	5271d 04h	/socgen/trunk/
10	added impact_bat to generate svf files	jt_eaton	5271d 05h	/socgen/trunk/
9	updated build_cmp and cleaned up fpga script added more utility tools	jt_eaton	5273d 06h	/socgen/trunk/
8	fixed loop sim, now pick up ROM_WORDS from sw dir	jt_eaton	5275d 06h	/socgen/trunk/
7	changed loop to use subroutines fixed typo on variants name	jt_eaton	5276d 06h	/socgen/trunk/
6	added pic_micro from minirisc project with design to run code on a digilent Basys board	jt_eaton	5280d 02h	/socgen/trunk/
5	added testbench and generic clock model	jt_eaton	5281d 07h	/socgen/trunk/
4	added generic model for single ended generic pad	jt_eaton	5281d 07h	/socgen/trunk/
3	started bin and lib directories, added install instructions for ubuntu 9.04	jt_eaton	5281d 20h	/socgen/trunk/
2	added starting docs	jt_eaton	5283d 04h	/socgen/trunk/
1	The project and the structure was created	root	5283d 17h	/socgen/trunk/