URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] - Rev 76

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Rev	Log message	Author	Age	Path
76	added wave.save files now generate sims Makefile and params.sim leave sim log and vcd files in sim/run/directory	jt_eaton	4998d 17h	/socgen/trunk/
75	added linting using verilator	jt_eaton	5002d 09h	/socgen/trunk/
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	5007d 14h	/socgen/trunk/
73	removed dup png files	jt_eaton	5015d 14h	/socgen/trunk/
72	split T6502 into components moved io_module into seperate project removed liblists direct loads filelists for sims and coverage add hier type into xml files to generate verilog	jt_eaton	5015d 16h	/socgen/trunk/
71	ignore anything in work	jt_eaton	5022d 08h	/socgen/trunk/
70	ignore work	jt_eaton	5022d 09h	/socgen/trunk/
69	added work dir	jt_eaton	5022d 09h	/socgen/trunk/
68	moved to seperate components	jt_eaton	5025d 08h	/socgen/trunk/
67	updated installs	jt_eaton	5025d 08h	/socgen/trunk/
66	converted sims to use parameters added msp and 6502 software installs	jt_eaton	5026d 08h	/socgen/trunk/
65	added params.sim to sims updated install's	jt_eaton	5031d 08h	/socgen/trunk/
64	added support for Fedora 13	jt_eaton	5035d 07h	/socgen/trunk/
63	added install config for Ubuntu 10.10	jt_eaton	5035d 14h	/socgen/trunk/
62	fixed parameters from `defines	jt_eaton	5039d 06h	/socgen/trunk/
61	now generate dut files for coverage removed use of lndir	jt_eaton	5039d 07h	/socgen/trunk/
60	moved alu_logic into seperate component	jt_eaton	5039d 19h	/socgen/trunk/
59	added filelist.core to syn dirs to customize core	jt_eaton	5039d 19h	/socgen/trunk/
58	removed old Makefiles	jt_eaton	5040d 10h	/socgen/trunk/
57	Now generate all filelists from xml files	jt_eaton	5040d 10h	/socgen/trunk/

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[/] [socgen/] [trunk/] - Rev 76

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