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[/] [socgen/] [trunk/] - Rev 94

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Rev Log message Author Age Path
94 socgen now supports both sim and syn views
now allow each xml file to set its destination
jt_eaton 4801d 02h /socgen/trunk/
93 build scripts now support model views
linting and coverage starting to work again
jt_eaton 4813d 15h /socgen/trunk/
92 all testbenchs now built from /sim/xml files
bench /models now in Testbench
jt_eaton 4818d 16h /socgen/trunk/
91 fixed all sims, coverage not working jt_eaton 4826d 10h /socgen/trunk/
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 4827d 02h /socgen/trunk/
89 removed unneeded debug directories jt_eaton 4848d 11h /socgen/trunk/
88 added xml files for test benches
added gEDA sym sch starter templates
jt_eaton 4848d 11h /socgen/trunk/
87 removed prebuilt geda schematics and symbols jt_eaton 4859d 04h /socgen/trunk/
86 split out all fpgas into families
added fpga pad_ring level
jt_eaton 4867d 01h /socgen/trunk/
85 moved all synthesis into fpgas lib
fixed memory leak in recursive routines
jt_eaton 4874d 00h /socgen/trunk/
84 removed unneeded files jt_eaton 4924d 05h /socgen/trunk/
83 added design.soc files
xml files now 99% 1685 complient
jt_eaton 4924d 09h /socgen/trunk/
82 renmamed cde_synchronizers to cde_sync
added hierarchial dependency search
converted more xmp to follow ip-xact
jt_eaton 4939d 03h /socgen/trunk/
81 morphing xml files to use 1685
removed log directories
jt_eaton 4960d 10h /socgen/trunk/
80 now generate all sims and syns param and filelists for xml jt_eaton 4990d 01h /socgen/trunk/
79 removed unsupported code jt_eaton 4996d 05h /socgen/trunk/
78 removed unsupported fpga jt_eaton 4996d 05h /socgen/trunk/
77 now generate syn and cov Makefiles
leave log and out files in sim/run directory
jt_eaton 4996d 06h /socgen/trunk/
76 added wave.save files
now generate sims Makefile and params.sim
leave sim log and vcd files in sim/run/directory
jt_eaton 4998d 11h /socgen/trunk/
75 added linting using verilator jt_eaton 5002d 03h /socgen/trunk/

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