URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [doc/] [src/] [drawing/] - Rev 134

Rev	Log message	Author	Age	Path
134	Resynced database socgen now supports elaboration Bad news is that it is now alot slower.	jt_eaton	3375d 09h	/socgen/trunk/doc/src/drawing/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4275d 04h	/socgen/trunk/doc/src/drawing/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4336d 05h	/socgen/trunk/doc/src/drawing/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4706d 23h	/socgen/trunk/doc/src/drawing/
81	morphing xml files to use 1685 removed log directories	jt_eaton	5012d 06h	/socgen/trunk/doc/src/drawing/
65	added params.sim to sims updated install's	jt_eaton	5083d 00h	/socgen/trunk/doc/src/drawing/
56	soc_builder now builds verilog from xml files	jt_eaton	5097d 10h	/socgen/trunk/doc/src/drawing/
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5103d 01h	/socgen/trunk/doc/src/drawing/
39	added io_probe to sims added boot rom into 6502 added T6502_control	jt_eaton	5182d 21h	/socgen/trunk/doc/src/drawing/
28	added T6502 processor added vga_char_ctrl	jt_eaton	5205d 09h	/socgen/trunk/doc/src/drawing/
27	added uart and ps2 host and models added more documentation	jt_eaton	5226d 23h	/socgen/trunk/doc/src/drawing/
20	added Nexys2 support expanded docs created tools directory	jt_eaton	5237d 21h	/socgen/trunk/doc/src/drawing/
19	added serial_xmit module updated and added docs	jt_eaton	5245d 03h	/socgen/trunk/doc/src/drawing/