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URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [doc/] [src/] [guides/] - Rev 128

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Rev	Log message	Author	Age	Path
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	4009d 06h	/socgen/trunk/doc/src/guides/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4222d 01h	/socgen/trunk/doc/src/guides/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4371d 00h	/socgen/trunk/doc/src/guides/
103	added user guide resynced to local repository	jt_eaton	4589d 02h	/socgen/trunk/doc/src/guides/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4852d 23h	/socgen/trunk/doc/src/guides/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4925d 20h	/socgen/trunk/doc/src/guides/
81	morphing xml files to use 1685 removed log directories	jt_eaton	5012d 06h	/socgen/trunk/doc/src/guides/
80	now generate all sims and syns param and filelists for xml	jt_eaton	5041d 21h	/socgen/trunk/doc/src/guides/
56	soc_builder now builds verilog from xml files	jt_eaton	5097d 10h	/socgen/trunk/doc/src/guides/
54	now set up fpga targets from xml files	jt_eaton	5100d 07h	/socgen/trunk/doc/src/guides/
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5103d 01h	/socgen/trunk/doc/src/guides/
28	added T6502 processor added vga_char_ctrl	jt_eaton	5205d 09h	/socgen/trunk/doc/src/guides/
27	added uart and ps2 host and models added more documentation	jt_eaton	5226d 23h	/socgen/trunk/doc/src/guides/
20	added Nexys2 support expanded docs created tools directory	jt_eaton	5237d 21h	/socgen/trunk/doc/src/guides/
19	added serial_xmit module updated and added docs	jt_eaton	5245d 03h	/socgen/trunk/doc/src/guides/

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