URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [doc/] [src/] [guides/] - Rev 124

Rev	Log message	Author	Age	Path
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4438d 07h	/socgen/trunk/doc/src/guides/
103	added user guide resynced to local repository	jt_eaton	4656d 08h	/socgen/trunk/doc/src/guides/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4920d 06h	/socgen/trunk/doc/src/guides/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4993d 03h	/socgen/trunk/doc/src/guides/
81	morphing xml files to use 1685 removed log directories	jt_eaton	5079d 13h	/socgen/trunk/doc/src/guides/
80	now generate all sims and syns param and filelists for xml	jt_eaton	5109d 04h	/socgen/trunk/doc/src/guides/
56	soc_builder now builds verilog from xml files	jt_eaton	5164d 17h	/socgen/trunk/doc/src/guides/
54	now set up fpga targets from xml files	jt_eaton	5167d 14h	/socgen/trunk/doc/src/guides/
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5170d 08h	/socgen/trunk/doc/src/guides/
28	added T6502 processor added vga_char_ctrl	jt_eaton	5272d 16h	/socgen/trunk/doc/src/guides/
27	added uart and ps2 host and models added more documentation	jt_eaton	5294d 06h	/socgen/trunk/doc/src/guides/
20	added Nexys2 support expanded docs created tools directory	jt_eaton	5305d 04h	/socgen/trunk/doc/src/guides/
19	added serial_xmit module updated and added docs	jt_eaton	5312d 10h	/socgen/trunk/doc/src/guides/