URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [doc/] [src/] [guides/] - Rev 124

Rev	Log message	Author	Age	Path
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4296d 08h	/socgen/trunk/doc/src/guides/
103	added user guide resynced to local repository	jt_eaton	4514d 09h	/socgen/trunk/doc/src/guides/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4778d 07h	/socgen/trunk/doc/src/guides/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4851d 04h	/socgen/trunk/doc/src/guides/
81	morphing xml files to use 1685 removed log directories	jt_eaton	4937d 14h	/socgen/trunk/doc/src/guides/
80	now generate all sims and syns param and filelists for xml	jt_eaton	4967d 05h	/socgen/trunk/doc/src/guides/
56	soc_builder now builds verilog from xml files	jt_eaton	5022d 18h	/socgen/trunk/doc/src/guides/
54	now set up fpga targets from xml files	jt_eaton	5025d 15h	/socgen/trunk/doc/src/guides/
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5028d 09h	/socgen/trunk/doc/src/guides/
28	added T6502 processor added vga_char_ctrl	jt_eaton	5130d 17h	/socgen/trunk/doc/src/guides/
27	added uart and ps2 host and models added more documentation	jt_eaton	5152d 07h	/socgen/trunk/doc/src/guides/
20	added Nexys2 support expanded docs created tools directory	jt_eaton	5163d 05h	/socgen/trunk/doc/src/guides/
19	added serial_xmit module updated and added docs	jt_eaton	5170d 11h	/socgen/trunk/doc/src/guides/