URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] - Rev 114

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4531d 22h	/socgen/trunk/tools/
113	started refactoring or1200	jt_eaton	4537d 15h	/socgen/trunk/tools/
112	added more test sims removed unneeded files	jt_eaton	4547d 03h	/socgen/trunk/tools/
110	split out more ip-xact components added sw sources	jt_eaton	4560d 19h	/socgen/trunk/tools/
107	added designCfg files to all modules	jt_eaton	4565d 04h	/socgen/trunk/tools/
106	checked in orp_soc project step 2	jt_eaton	4570d 21h	/socgen/trunk/tools/
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4575d 18h	/socgen/trunk/tools/
103	added user guide resynced to local repository	jt_eaton	4595d 19h	/socgen/trunk/tools/
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4658d 16h	/socgen/trunk/tools/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4670d 23h	/socgen/trunk/tools/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4713d 16h	/socgen/trunk/tools/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4749d 21h	/socgen/trunk/tools/
96	hierConnections now create ports	jt_eaton	4823d 17h	/socgen/trunk/tools/
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4832d 15h	/socgen/trunk/tools/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4859d 16h	/socgen/trunk/tools/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4872d 05h	/socgen/trunk/tools/
92	all testbenchs now built from /sim/xml files bench /models now in Testbench	jt_eaton	4877d 06h	/socgen/trunk/tools/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4885d 16h	/socgen/trunk/tools/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4907d 01h	/socgen/trunk/tools/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4925d 15h	/socgen/trunk/tools/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] - Rev 114

Filtering Options