URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] - Rev 121

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Rev	Log message	Author	Age	Path
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4289d 05h	/socgen/trunk/tools/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4307d 05h	/socgen/trunk/tools/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4341d 23h	/socgen/trunk/tools/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4377d 08h	/socgen/trunk/tools/
117	added yellow pages tools	jt_eaton	4405d 03h	/socgen/trunk/tools/
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4440d 00h	/socgen/trunk/tools/
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4484d 05h	/socgen/trunk/tools/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4496d 05h	/socgen/trunk/tools/
113	started refactoring or1200	jt_eaton	4501d 21h	/socgen/trunk/tools/
112	added more test sims removed unneeded files	jt_eaton	4511d 10h	/socgen/trunk/tools/
110	split out more ip-xact components added sw sources	jt_eaton	4525d 02h	/socgen/trunk/tools/
107	added designCfg files to all modules	jt_eaton	4529d 10h	/socgen/trunk/tools/
106	checked in orp_soc project step 2	jt_eaton	4535d 03h	/socgen/trunk/tools/
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4540d 00h	/socgen/trunk/tools/
103	added user guide resynced to local repository	jt_eaton	4560d 01h	/socgen/trunk/tools/
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4622d 22h	/socgen/trunk/tools/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4635d 06h	/socgen/trunk/tools/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4677d 22h	/socgen/trunk/tools/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4714d 03h	/socgen/trunk/tools/
96	hierConnections now create ports	jt_eaton	4787d 23h	/socgen/trunk/tools/

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[/] [socgen/] [trunk/] [tools/] - Rev 121

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