URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] - Rev 130

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Rev	Log message	Author	Age	Path
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3477d 09h	/socgen/trunk/tools/
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3932d 15h	/socgen/trunk/tools/
127	final cleanup before DAC	jt_eaton	4047d 11h	/socgen/trunk/tools/
126	added mor1kx cleanup	jt_eaton	4100d 16h	/socgen/trunk/tools/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4145d 10h	/socgen/trunk/tools/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4198d 13h	/socgen/trunk/tools/
123	added support for ubuntu 12.10	jt_eaton	4213d 06h	/socgen/trunk/tools/
122	Moved Nexys2 from opencores.org to digilentinc.com Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components	jt_eaton	4221d 08h	/socgen/trunk/tools/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4241d 14h	/socgen/trunk/tools/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4259d 15h	/socgen/trunk/tools/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4294d 09h	/socgen/trunk/tools/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4329d 18h	/socgen/trunk/tools/
117	added yellow pages tools	jt_eaton	4357d 13h	/socgen/trunk/tools/
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4392d 10h	/socgen/trunk/tools/
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4436d 15h	/socgen/trunk/tools/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4448d 14h	/socgen/trunk/tools/
113	started refactoring or1200	jt_eaton	4454d 07h	/socgen/trunk/tools/
112	added more test sims removed unneeded files	jt_eaton	4463d 19h	/socgen/trunk/tools/
110	split out more ip-xact components added sw sources	jt_eaton	4477d 11h	/socgen/trunk/tools/
107	added designCfg files to all modules	jt_eaton	4481d 20h	/socgen/trunk/tools/

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[/] [socgen/] [trunk/] [tools/] - Rev 130

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