URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] - Rev 56

Rev	Log message	Author	Age	Path
56	soc_builder now builds verilog from xml files	jt_eaton	5045d 13h	/socgen/trunk/tools/
54	now set up fpga targets from xml files	jt_eaton	5048d 11h	/socgen/trunk/tools/
50	clean up from last checkin	jt_eaton	5051d 01h	/socgen/trunk/tools/
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5051d 04h	/socgen/trunk/tools/
48	added support for covered code checking	jt_eaton	5073d 10h	/socgen/trunk/tools/
46	removed hard coded component names from design files define file is always defines.v top level is always top.v	jt_eaton	5087d 13h	/socgen/trunk/tools/
41	added kim-1 design and program now support Nexys2 sdram	jt_eaton	5122d 12h	/socgen/trunk/tools/
28	added T6502 processor added vga_char_ctrl	jt_eaton	5153d 12h	/socgen/trunk/tools/
27	added uart and ps2 host and models added more documentation	jt_eaton	5175d 03h	/socgen/trunk/tools/
26	moved install instructions from doc -> tools added scripts to install or32 gnu toolchain and fizzim state tool	jt_eaton	5183d 15h	/socgen/trunk/tools/
25	updated for ubuntu 10.4 install	jt_eaton	5184d 07h	/socgen/trunk/tools/
23	fixed typos and ommisions	jt_eaton	5185d 11h	/socgen/trunk/tools/
22	added install instructions for ubuntu 10.4	jt_eaton	5185d 12h	/socgen/trunk/tools/
20	added Nexys2 support expanded docs created tools directory	jt_eaton	5186d 00h	/socgen/trunk/tools/