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[/] [socgen/] [trunk/] [tools/] - Rev 65

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Rev Log message Author Age Path
65 added params.sim to sims
updated install's
jt_eaton 5083d 00h /socgen/trunk/tools/
64 added support for Fedora 13 jt_eaton 5086d 22h /socgen/trunk/tools/
63 added install config for Ubuntu 10.10 jt_eaton 5087d 05h /socgen/trunk/tools/
61 now generate dut files for coverage
removed use of lndir
jt_eaton 5090d 23h /socgen/trunk/tools/
59 added filelist.core to syn dirs to customize core jt_eaton 5091d 10h /socgen/trunk/tools/
57 Now generate all filelists from xml files jt_eaton 5092d 02h /socgen/trunk/tools/
56 soc_builder now builds verilog from xml files jt_eaton 5097d 10h /socgen/trunk/tools/
54 now set up fpga targets from xml files jt_eaton 5100d 07h /socgen/trunk/tools/
50 clean up from last checkin jt_eaton 5102d 22h /socgen/trunk/tools/
49 added covered code coverage
added xml descriptors
added soc_Link tool
jt_eaton 5103d 01h /socgen/trunk/tools/
48 added support for covered code checking jt_eaton 5125d 07h /socgen/trunk/tools/
46 removed hard coded component names from design files
define file is always defines.v
top level is always top.v
jt_eaton 5139d 10h /socgen/trunk/tools/
41 added kim-1 design and program
now support Nexys2 sdram
jt_eaton 5174d 08h /socgen/trunk/tools/
28 added T6502 processor
added vga_char_ctrl
jt_eaton 5205d 09h /socgen/trunk/tools/
27 added uart and ps2 host and models
added more documentation
jt_eaton 5226d 23h /socgen/trunk/tools/
26 moved install instructions from doc -> tools
added scripts to install or32 gnu toolchain and fizzim state tool
jt_eaton 5235d 12h /socgen/trunk/tools/
25 updated for ubuntu 10.4 install jt_eaton 5236d 04h /socgen/trunk/tools/
23 fixed typos and ommisions jt_eaton 5237d 07h /socgen/trunk/tools/
22 added install instructions for ubuntu 10.4 jt_eaton 5237d 08h /socgen/trunk/tools/
20 added Nexys2 support
expanded docs
created tools directory
jt_eaton 5237d 21h /socgen/trunk/tools/

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