OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] - Rev 94

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
94 socgen now supports both sim and syn views
now allow each xml file to set its destination
jt_eaton 4801d 02h /socgen/trunk/tools/
93 build scripts now support model views
linting and coverage starting to work again
jt_eaton 4813d 15h /socgen/trunk/tools/
92 all testbenchs now built from /sim/xml files
bench /models now in Testbench
jt_eaton 4818d 16h /socgen/trunk/tools/
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 4827d 02h /socgen/trunk/tools/
88 added xml files for test benches
added gEDA sym sch starter templates
jt_eaton 4848d 11h /socgen/trunk/tools/
86 split out all fpgas into families
added fpga pad_ring level
jt_eaton 4867d 01h /socgen/trunk/tools/
85 moved all synthesis into fpgas lib
fixed memory leak in recursive routines
jt_eaton 4874d 00h /socgen/trunk/tools/
84 removed unneeded files jt_eaton 4924d 05h /socgen/trunk/tools/
83 added design.soc files
xml files now 99% 1685 complient
jt_eaton 4924d 09h /socgen/trunk/tools/
82 renmamed cde_synchronizers to cde_sync
added hierarchial dependency search
converted more xmp to follow ip-xact
jt_eaton 4939d 03h /socgen/trunk/tools/
81 morphing xml files to use 1685
removed log directories
jt_eaton 4960d 10h /socgen/trunk/tools/
80 now generate all sims and syns param and filelists for xml jt_eaton 4990d 01h /socgen/trunk/tools/
76 added wave.save files
now generate sims Makefile and params.sim
leave sim log and vcd files in sim/run/directory
jt_eaton 4998d 11h /socgen/trunk/tools/
75 added linting using verilator jt_eaton 5002d 03h /socgen/trunk/tools/
74 split out sw Makefile into projects /bin
split out _cpu into seperate component
jt_eaton 5007d 09h /socgen/trunk/tools/
72 split T6502 into components
moved io_module into seperate project
removed liblists
direct loads filelists for sims and coverage
add hier type into xml files to generate verilog
jt_eaton 5015d 10h /socgen/trunk/tools/
67 updated installs jt_eaton 5025d 03h /socgen/trunk/tools/
66 converted sims to use parameters
added msp and 6502 software installs
jt_eaton 5026d 02h /socgen/trunk/tools/
65 added params.sim to sims
updated install's
jt_eaton 5031d 03h /socgen/trunk/tools/
64 added support for Fedora 13 jt_eaton 5035d 02h /socgen/trunk/tools/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.