URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] - Rev 95

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4805d 06h	/socgen/trunk/tools/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4832d 07h	/socgen/trunk/tools/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4844d 19h	/socgen/trunk/tools/
92	all testbenchs now built from /sim/xml files bench /models now in Testbench	jt_eaton	4849d 20h	/socgen/trunk/tools/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4858d 07h	/socgen/trunk/tools/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4879d 15h	/socgen/trunk/tools/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4898d 05h	/socgen/trunk/tools/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4905d 04h	/socgen/trunk/tools/
84	removed unneeded files	jt_eaton	4955d 09h	/socgen/trunk/tools/
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	4955d 14h	/socgen/trunk/tools/
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	4970d 08h	/socgen/trunk/tools/
81	morphing xml files to use 1685 removed log directories	jt_eaton	4991d 14h	/socgen/trunk/tools/
80	now generate all sims and syns param and filelists for xml	jt_eaton	5021d 05h	/socgen/trunk/tools/
76	added wave.save files now generate sims Makefile and params.sim leave sim log and vcd files in sim/run/directory	jt_eaton	5029d 15h	/socgen/trunk/tools/
75	added linting using verilator	jt_eaton	5033d 08h	/socgen/trunk/tools/
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	5038d 13h	/socgen/trunk/tools/
72	split T6502 into components moved io_module into seperate project removed liblists direct loads filelists for sims and coverage add hier type into xml files to generate verilog	jt_eaton	5046d 15h	/socgen/trunk/tools/
67	updated installs	jt_eaton	5056d 07h	/socgen/trunk/tools/
66	converted sims to use parameters added msp and 6502 software installs	jt_eaton	5057d 07h	/socgen/trunk/tools/
65	added params.sim to sims updated install's	jt_eaton	5062d 07h	/socgen/trunk/tools/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] - Rev 95

Filtering Options