URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] - Rev 97

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Rev	Log message	Author	Age	Path
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4674d 22h	/socgen/trunk/tools/
96	hierConnections now create ports	jt_eaton	4748d 19h	/socgen/trunk/tools/
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4757d 16h	/socgen/trunk/tools/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4784d 18h	/socgen/trunk/tools/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4797d 06h	/socgen/trunk/tools/
92	all testbenchs now built from /sim/xml files bench /models now in Testbench	jt_eaton	4802d 07h	/socgen/trunk/tools/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4810d 18h	/socgen/trunk/tools/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4832d 02h	/socgen/trunk/tools/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4850d 16h	/socgen/trunk/tools/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4857d 15h	/socgen/trunk/tools/
84	removed unneeded files	jt_eaton	4907d 20h	/socgen/trunk/tools/
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	4908d 00h	/socgen/trunk/tools/
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	4922d 19h	/socgen/trunk/tools/
81	morphing xml files to use 1685 removed log directories	jt_eaton	4944d 01h	/socgen/trunk/tools/
80	now generate all sims and syns param and filelists for xml	jt_eaton	4973d 16h	/socgen/trunk/tools/
76	added wave.save files now generate sims Makefile and params.sim leave sim log and vcd files in sim/run/directory	jt_eaton	4982d 02h	/socgen/trunk/tools/
75	added linting using verilator	jt_eaton	4985d 19h	/socgen/trunk/tools/
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	4991d 00h	/socgen/trunk/tools/
72	split T6502 into components moved io_module into seperate project removed liblists direct loads filelists for sims and coverage add hier type into xml files to generate verilog	jt_eaton	4999d 02h	/socgen/trunk/tools/
67	updated installs	jt_eaton	5008d 18h	/socgen/trunk/tools/

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[/] [socgen/] [trunk/] [tools/] - Rev 97

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