URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 117

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Rev	Log message	Author	Age	Path
117	added yellow pages tools	jt_eaton	4492d 22h	/socgen/trunk/tools/bin/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4584d 00h	/socgen/trunk/tools/bin/
113	started refactoring or1200	jt_eaton	4589d 16h	/socgen/trunk/tools/bin/
112	added more test sims removed unneeded files	jt_eaton	4599d 05h	/socgen/trunk/tools/bin/
106	checked in orp_soc project step 2	jt_eaton	4622d 23h	/socgen/trunk/tools/bin/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4723d 01h	/socgen/trunk/tools/bin/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4765d 17h	/socgen/trunk/tools/bin/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4801d 23h	/socgen/trunk/tools/bin/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4911d 18h	/socgen/trunk/tools/bin/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4924d 06h	/socgen/trunk/tools/bin/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4937d 18h	/socgen/trunk/tools/bin/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4959d 02h	/socgen/trunk/tools/bin/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4977d 16h	/socgen/trunk/tools/bin/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4984d 15h	/socgen/trunk/tools/bin/
84	removed unneeded files	jt_eaton	5034d 20h	/socgen/trunk/tools/bin/
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	5035d 01h	/socgen/trunk/tools/bin/
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	5049d 19h	/socgen/trunk/tools/bin/
81	morphing xml files to use 1685 removed log directories	jt_eaton	5071d 01h	/socgen/trunk/tools/bin/
80	now generate all sims and syns param and filelists for xml	jt_eaton	5100d 16h	/socgen/trunk/tools/bin/
76	added wave.save files now generate sims Makefile and params.sim leave sim log and vcd files in sim/run/directory	jt_eaton	5109d 02h	/socgen/trunk/tools/bin/

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[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 117

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