URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 124

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Rev	Log message	Author	Age	Path
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4203d 20h	/socgen/trunk/tools/bin/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4264d 22h	/socgen/trunk/tools/bin/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4299d 16h	/socgen/trunk/tools/bin/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4335d 01h	/socgen/trunk/tools/bin/
117	added yellow pages tools	jt_eaton	4362d 20h	/socgen/trunk/tools/bin/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4453d 21h	/socgen/trunk/tools/bin/
113	started refactoring or1200	jt_eaton	4459d 14h	/socgen/trunk/tools/bin/
112	added more test sims removed unneeded files	jt_eaton	4469d 03h	/socgen/trunk/tools/bin/
106	checked in orp_soc project step 2	jt_eaton	4492d 20h	/socgen/trunk/tools/bin/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4592d 22h	/socgen/trunk/tools/bin/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4635d 15h	/socgen/trunk/tools/bin/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4671d 20h	/socgen/trunk/tools/bin/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4781d 15h	/socgen/trunk/tools/bin/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4794d 04h	/socgen/trunk/tools/bin/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4807d 15h	/socgen/trunk/tools/bin/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4829d 00h	/socgen/trunk/tools/bin/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4847d 14h	/socgen/trunk/tools/bin/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4854d 13h	/socgen/trunk/tools/bin/
84	removed unneeded files	jt_eaton	4904d 18h	/socgen/trunk/tools/bin/
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	4904d 22h	/socgen/trunk/tools/bin/

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[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 124

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