URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 133

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Rev	Log message	Author	Age	Path
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3481d 03h	/socgen/trunk/tools/bin/
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3584d 21h	/socgen/trunk/tools/bin/
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	4040d 03h	/socgen/trunk/tools/bin/
126	added mor1kx cleanup	jt_eaton	4208d 04h	/socgen/trunk/tools/bin/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4252d 22h	/socgen/trunk/tools/bin/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4306d 01h	/socgen/trunk/tools/bin/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4367d 02h	/socgen/trunk/tools/bin/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4401d 21h	/socgen/trunk/tools/bin/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4437d 06h	/socgen/trunk/tools/bin/
117	added yellow pages tools	jt_eaton	4465d 01h	/socgen/trunk/tools/bin/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4556d 02h	/socgen/trunk/tools/bin/
113	started refactoring or1200	jt_eaton	4561d 18h	/socgen/trunk/tools/bin/
112	added more test sims removed unneeded files	jt_eaton	4571d 07h	/socgen/trunk/tools/bin/
106	checked in orp_soc project step 2	jt_eaton	4595d 01h	/socgen/trunk/tools/bin/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4695d 03h	/socgen/trunk/tools/bin/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4737d 20h	/socgen/trunk/tools/bin/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4774d 01h	/socgen/trunk/tools/bin/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4883d 20h	/socgen/trunk/tools/bin/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4896d 08h	/socgen/trunk/tools/bin/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4909d 20h	/socgen/trunk/tools/bin/

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[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 133

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