URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 57

Rev	Log message	Author	Age	Path
57	Now generate all filelists from xml files	jt_eaton	5042d 08h	/socgen/trunk/tools/bin/
56	soc_builder now builds verilog from xml files	jt_eaton	5047d 16h	/socgen/trunk/tools/bin/
54	now set up fpga targets from xml files	jt_eaton	5050d 14h	/socgen/trunk/tools/bin/
50	clean up from last checkin	jt_eaton	5053d 04h	/socgen/trunk/tools/bin/
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5053d 07h	/socgen/trunk/tools/bin/
48	added support for covered code checking	jt_eaton	5075d 13h	/socgen/trunk/tools/bin/
46	removed hard coded component names from design files define file is always defines.v top level is always top.v	jt_eaton	5089d 17h	/socgen/trunk/tools/bin/
41	added kim-1 design and program now support Nexys2 sdram	jt_eaton	5124d 15h	/socgen/trunk/tools/bin/
20	added Nexys2 support expanded docs created tools directory	jt_eaton	5188d 03h	/socgen/trunk/tools/bin/