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[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 81

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Rev Log message Author Age Path
81 morphing xml files to use 1685
removed log directories		 jt_eaton 4960d 11h /socgen/trunk/tools/bin/
80 now generate all sims and syns param and filelists for xml jt_eaton 4990d 02h /socgen/trunk/tools/bin/
76 added wave.save files
now generate sims Makefile and params.sim
leave sim log and vcd files in sim/run/directory		 jt_eaton 4998d 13h /socgen/trunk/tools/bin/
75 added linting using verilator jt_eaton 5002d 05h /socgen/trunk/tools/bin/
74 split out sw Makefile into projects /bin
split out _cpu into seperate component		 jt_eaton 5007d 10h /socgen/trunk/tools/bin/
72 split T6502 into components
moved io_module into seperate project
removed liblists
direct loads filelists for sims and coverage
add hier type into xml files to generate verilog		 jt_eaton 5015d 12h /socgen/trunk/tools/bin/
67 updated installs jt_eaton 5025d 05h /socgen/trunk/tools/bin/
66 converted sims to use parameters
added msp and 6502 software installs		 jt_eaton 5026d 04h /socgen/trunk/tools/bin/
65 added params.sim to sims
updated install's		 jt_eaton 5031d 05h /socgen/trunk/tools/bin/
61 now generate dut files for coverage
removed use of lndir		 jt_eaton 5039d 04h /socgen/trunk/tools/bin/
59 added filelist.core to syn dirs to customize core jt_eaton 5039d 15h /socgen/trunk/tools/bin/
57 Now generate all filelists from xml files jt_eaton 5040d 06h /socgen/trunk/tools/bin/
56 soc_builder now builds verilog from xml files jt_eaton 5045d 15h /socgen/trunk/tools/bin/
54 now set up fpga targets from xml files jt_eaton 5048d 12h /socgen/trunk/tools/bin/
50 clean up from last checkin jt_eaton 5051d 03h /socgen/trunk/tools/bin/
49 added covered code coverage
added xml descriptors
added soc_Link tool		 jt_eaton 5051d 06h /socgen/trunk/tools/bin/
48 added support for covered code checking jt_eaton 5073d 12h /socgen/trunk/tools/bin/
46 removed hard coded component names from design files
define file is always defines.v
top level is always top.v		 jt_eaton 5087d 15h /socgen/trunk/tools/bin/
41 added kim-1 design and program
now support Nexys2 sdram		 jt_eaton 5122d 13h /socgen/trunk/tools/bin/
20 added Nexys2 support
expanded docs
created tools directory		 jt_eaton 5186d 02h /socgen/trunk/tools/bin/

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