URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 92

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Rev	Log message	Author	Age	Path
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4828d 07h	/socgen/trunk/tools/bin/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4849d 16h	/socgen/trunk/tools/bin/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4868d 06h	/socgen/trunk/tools/bin/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4875d 05h	/socgen/trunk/tools/bin/
84	removed unneeded files	jt_eaton	4925d 10h	/socgen/trunk/tools/bin/
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	4925d 14h	/socgen/trunk/tools/bin/
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	4940d 08h	/socgen/trunk/tools/bin/
81	morphing xml files to use 1685 removed log directories	jt_eaton	4961d 14h	/socgen/trunk/tools/bin/
80	now generate all sims and syns param and filelists for xml	jt_eaton	4991d 05h	/socgen/trunk/tools/bin/
76	added wave.save files now generate sims Makefile and params.sim leave sim log and vcd files in sim/run/directory	jt_eaton	4999d 16h	/socgen/trunk/tools/bin/
75	added linting using verilator	jt_eaton	5003d 08h	/socgen/trunk/tools/bin/
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	5008d 13h	/socgen/trunk/tools/bin/
72	split T6502 into components moved io_module into seperate project removed liblists direct loads filelists for sims and coverage add hier type into xml files to generate verilog	jt_eaton	5016d 15h	/socgen/trunk/tools/bin/
67	updated installs	jt_eaton	5026d 08h	/socgen/trunk/tools/bin/
66	converted sims to use parameters added msp and 6502 software installs	jt_eaton	5027d 07h	/socgen/trunk/tools/bin/
65	added params.sim to sims updated install's	jt_eaton	5032d 08h	/socgen/trunk/tools/bin/
61	now generate dut files for coverage removed use of lndir	jt_eaton	5040d 07h	/socgen/trunk/tools/bin/
59	added filelist.core to syn dirs to customize core	jt_eaton	5040d 18h	/socgen/trunk/tools/bin/
57	Now generate all filelists from xml files	jt_eaton	5041d 10h	/socgen/trunk/tools/bin/
56	soc_builder now builds verilog from xml files	jt_eaton	5046d 18h	/socgen/trunk/tools/bin/

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[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 92

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