URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [synthesys/] - Rev 131

Rev	Log message	Author	Age	Path
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3382d 16h	/socgen/trunk/tools/synthesys/
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3486d 09h	/socgen/trunk/tools/synthesys/
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3941d 16h	/socgen/trunk/tools/synthesys/
127	final cleanup before DAC	jt_eaton	4056d 12h	/socgen/trunk/tools/synthesys/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4154d 11h	/socgen/trunk/tools/synthesys/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4207d 14h	/socgen/trunk/tools/synthesys/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4250d 15h	/socgen/trunk/tools/synthesys/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4268d 15h	/socgen/trunk/tools/synthesys/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4303d 09h	/socgen/trunk/tools/synthesys/