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[/] [socgen/] [trunk/] [tools/] [synthesys/] - Rev 134

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Rev Log message Author Age Path
134 Resynced database
socgen now supports elaboration
Bad news is that it is now alot slower.		 jt_eaton 3320d 03h /socgen/trunk/tools/synthesys/
133 Added Desing databases and foundation for elaborations tools jt_eaton 3363d 04h /socgen/trunk/tools/synthesys/
131 Added elaboration databases and tools
Added bus map creation tools		 jt_eaton 3395d 01h /socgen/trunk/tools/synthesys/
130 Dec 2014 major release
trimmed out some IP
replaced perl database with Berkeley		 jt_eaton 3498d 18h /socgen/trunk/tools/synthesys/
128 major cleanup
added toolflows for sim,syn,documentation,linting and verilog
added documentation tools		 jt_eaton 3954d 00h /socgen/trunk/tools/synthesys/
127 final cleanup before DAC jt_eaton 4068d 20h /socgen/trunk/tools/synthesys/
125 Added two new 6502 cores in www.6502.org

cleaned up sogen xml files and added module name control		 jt_eaton 4166d 19h /socgen/trunk/tools/synthesys/
124 beta release candidate 1
changed design.xml name
aligned schema with filesystem		 jt_eaton 4219d 22h /socgen/trunk/tools/synthesys/
121 cleaned up sims, added autogenerated test bench files
removed mrisc and experimental or1k code		 jt_eaton 4262d 23h /socgen/trunk/tools/synthesys/
120 clean up componentGenerators names and directories
sim + lint now synthesis TestBench		 jt_eaton 4281d 00h /socgen/trunk/tools/synthesys/
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace		 jt_eaton 4315d 18h /socgen/trunk/tools/synthesys/

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