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[/] [socgen/] [trunk/] [tools/] [sys/] - Rev 107

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Rev Log message Author Age Path
107 added designCfg files to all modules jt_eaton 4502d 04h /socgen/trunk/tools/sys/
104 fixed search in preprocessor script
added initial orp_soc project		 jt_eaton 4512d 18h /socgen/trunk/tools/sys/
103 added user guide
resynced to local repository		 jt_eaton 4532d 18h /socgen/trunk/tools/sys/
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT		 jt_eaton 4595d 15h /socgen/trunk/tools/sys/
100 created workspace prroject=fpga_mrisc for single compile
general cleanup		 jt_eaton 4607d 23h /socgen/trunk/tools/sys/
99 moved all projects into /projects/opencores.org
added build_register
added fizzim		 jt_eaton 4650d 15h /socgen/trunk/tools/sys/
97 changed sim run directory to icarus
added ise directory into syn
added _tb testbench file to all sims		 jt_eaton 4686d 21h /socgen/trunk/tools/sys/
96 hierConnections now create ports jt_eaton 4760d 17h /socgen/trunk/tools/sys/
95 added first cut at busdefs
added clock reset enable pads and jtag_rpc		 jt_eaton 4769d 15h /socgen/trunk/tools/sys/
94 socgen now supports both sim and syn views
now allow each xml file to set its destination		 jt_eaton 4796d 16h /socgen/trunk/tools/sys/
93 build scripts now support model views
linting and coverage starting to work again		 jt_eaton 4809d 04h /socgen/trunk/tools/sys/
92 all testbenchs now built from /sim/xml files
bench /models now in Testbench		 jt_eaton 4814d 05h /socgen/trunk/tools/sys/
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 4822d 16h /socgen/trunk/tools/sys/

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