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[/] [socgen/] [trunk/] [tools/] [sys/] - Rev 118

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Rev	Log message	Author	Age	Path
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4361d 18h	/socgen/trunk/tools/sys/
117	added yellow pages tools	jt_eaton	4389d 13h	/socgen/trunk/tools/sys/
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4424d 10h	/socgen/trunk/tools/sys/
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4468d 14h	/socgen/trunk/tools/sys/
110	split out more ip-xact components added sw sources	jt_eaton	4509d 11h	/socgen/trunk/tools/sys/
107	added designCfg files to all modules	jt_eaton	4513d 20h	/socgen/trunk/tools/sys/
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4524d 10h	/socgen/trunk/tools/sys/
103	added user guide resynced to local repository	jt_eaton	4544d 10h	/socgen/trunk/tools/sys/
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4607d 07h	/socgen/trunk/tools/sys/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4619d 15h	/socgen/trunk/tools/sys/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4662d 07h	/socgen/trunk/tools/sys/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4698d 13h	/socgen/trunk/tools/sys/
96	hierConnections now create ports	jt_eaton	4772d 09h	/socgen/trunk/tools/sys/
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4781d 07h	/socgen/trunk/tools/sys/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4808d 08h	/socgen/trunk/tools/sys/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4820d 20h	/socgen/trunk/tools/sys/
92	all testbenchs now built from /sim/xml files bench /models now in Testbench	jt_eaton	4825d 21h	/socgen/trunk/tools/sys/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4834d 08h	/socgen/trunk/tools/sys/

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