URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [sys/] - Rev 127

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
127	final cleanup before DAC	jt_eaton	4067d 22h	/socgen/trunk/tools/sys/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4165d 21h	/socgen/trunk/tools/sys/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4219d 00h	/socgen/trunk/tools/sys/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4262d 01h	/socgen/trunk/tools/sys/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4280d 01h	/socgen/trunk/tools/sys/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4314d 20h	/socgen/trunk/tools/sys/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4350d 05h	/socgen/trunk/tools/sys/
117	added yellow pages tools	jt_eaton	4378d 00h	/socgen/trunk/tools/sys/
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4412d 21h	/socgen/trunk/tools/sys/
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4457d 01h	/socgen/trunk/tools/sys/
110	split out more ip-xact components added sw sources	jt_eaton	4497d 22h	/socgen/trunk/tools/sys/
107	added designCfg files to all modules	jt_eaton	4502d 07h	/socgen/trunk/tools/sys/
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4512d 21h	/socgen/trunk/tools/sys/
103	added user guide resynced to local repository	jt_eaton	4532d 21h	/socgen/trunk/tools/sys/
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4595d 18h	/socgen/trunk/tools/sys/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4608d 02h	/socgen/trunk/tools/sys/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4650d 19h	/socgen/trunk/tools/sys/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4687d 00h	/socgen/trunk/tools/sys/
96	hierConnections now create ports	jt_eaton	4760d 20h	/socgen/trunk/tools/sys/
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4769d 18h	/socgen/trunk/tools/sys/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [sys/] - Rev 127

Filtering Options