URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [sys/] - Rev 135

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Rev	Log message	Author	Age	Path
135	resynced with socgen, Release V1.0.0 changed tool lic to apache 2.0	jt_eaton	2855d 15h	/socgen/trunk/tools/sys/
134	Resynced database socgen now supports elaboration Bad news is that it is now alot slower.	jt_eaton	3365d 17h	/socgen/trunk/tools/sys/
133	Added Desing databases and foundation for elaborations tools	jt_eaton	3408d 18h	/socgen/trunk/tools/sys/
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3440d 14h	/socgen/trunk/tools/sys/
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3544d 08h	/socgen/trunk/tools/sys/
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3999d 14h	/socgen/trunk/tools/sys/
127	final cleanup before DAC	jt_eaton	4114d 10h	/socgen/trunk/tools/sys/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4212d 09h	/socgen/trunk/tools/sys/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4265d 12h	/socgen/trunk/tools/sys/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4308d 13h	/socgen/trunk/tools/sys/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4326d 13h	/socgen/trunk/tools/sys/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4361d 08h	/socgen/trunk/tools/sys/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4396d 17h	/socgen/trunk/tools/sys/
117	added yellow pages tools	jt_eaton	4424d 12h	/socgen/trunk/tools/sys/
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4459d 09h	/socgen/trunk/tools/sys/
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4503d 13h	/socgen/trunk/tools/sys/
110	split out more ip-xact components added sw sources	jt_eaton	4544d 10h	/socgen/trunk/tools/sys/
107	added designCfg files to all modules	jt_eaton	4548d 19h	/socgen/trunk/tools/sys/
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4559d 09h	/socgen/trunk/tools/sys/
103	added user guide resynced to local repository	jt_eaton	4579d 09h	/socgen/trunk/tools/sys/

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[/] [socgen/] [trunk/] [tools/] [sys/] - Rev 135

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