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[/] [socgen/] [trunk/] [tools/] [verilog/] - Rev 121

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Rev Log message Author Age Path
121 cleaned up sims, added autogenerated test bench files
removed mrisc and experimental or1k code
jt_eaton 4262d 02h /socgen/trunk/tools/verilog/
120 clean up componentGenerators names and directories
sim + lint now synthesis TestBench
jt_eaton 4280d 02h /socgen/trunk/tools/verilog/
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace
jt_eaton 4314d 20h /socgen/trunk/tools/verilog/

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