URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [verilog/] - Rev 128

Rev	Log message	Author	Age	Path
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3964d 03h	/socgen/trunk/tools/verilog/
127	final cleanup before DAC	jt_eaton	4079d 00h	/socgen/trunk/tools/verilog/
126	added mor1kx cleanup	jt_eaton	4132d 04h	/socgen/trunk/tools/verilog/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4176d 22h	/socgen/trunk/tools/verilog/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4230d 01h	/socgen/trunk/tools/verilog/
123	added support for ubuntu 12.10	jt_eaton	4244d 18h	/socgen/trunk/tools/verilog/
122	Moved Nexys2 from opencores.org to digilentinc.com Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components	jt_eaton	4252d 21h	/socgen/trunk/tools/verilog/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4273d 03h	/socgen/trunk/tools/verilog/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4291d 03h	/socgen/trunk/tools/verilog/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4325d 21h	/socgen/trunk/tools/verilog/