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[/] [socgen/] [trunk/] [tools/] [verilog/] - Rev 133

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Rev	Log message	Author	Age	Path
133	Added Desing databases and foundation for elaborations tools	jt_eaton	3356d 08h	/socgen/trunk/tools/verilog/
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3388d 05h	/socgen/trunk/tools/verilog/
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3491d 22h	/socgen/trunk/tools/verilog/
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3947d 04h	/socgen/trunk/tools/verilog/
127	final cleanup before DAC	jt_eaton	4062d 00h	/socgen/trunk/tools/verilog/
126	added mor1kx cleanup	jt_eaton	4115d 05h	/socgen/trunk/tools/verilog/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4159d 23h	/socgen/trunk/tools/verilog/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4213d 02h	/socgen/trunk/tools/verilog/
123	added support for ubuntu 12.10	jt_eaton	4227d 19h	/socgen/trunk/tools/verilog/
122	Moved Nexys2 from opencores.org to digilentinc.com Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components	jt_eaton	4235d 21h	/socgen/trunk/tools/verilog/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4256d 03h	/socgen/trunk/tools/verilog/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4274d 04h	/socgen/trunk/tools/verilog/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4308d 22h	/socgen/trunk/tools/verilog/

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