URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [yp/] - Rev 123

Rev	Log message	Author	Age	Path
122	Moved Nexys2 from opencores.org to digilentinc.com Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components	jt_eaton	4319d 19h	/socgen/trunk/tools/yp/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4340d 01h	/socgen/trunk/tools/yp/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4358d 02h	/socgen/trunk/tools/yp/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4392d 20h	/socgen/trunk/tools/yp/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4428d 05h	/socgen/trunk/tools/yp/
117	added yellow pages tools	jt_eaton	4456d 00h	/socgen/trunk/tools/yp/