URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [yp/] - Rev 127

Rev	Log message	Author	Age	Path
127	final cleanup before DAC	jt_eaton	4067d 21h	/socgen/trunk/tools/yp/
126	added mor1kx cleanup	jt_eaton	4121d 02h	/socgen/trunk/tools/yp/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4165d 20h	/socgen/trunk/tools/yp/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4218d 23h	/socgen/trunk/tools/yp/
122	Moved Nexys2 from opencores.org to digilentinc.com Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components	jt_eaton	4241d 18h	/socgen/trunk/tools/yp/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4262d 00h	/socgen/trunk/tools/yp/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4280d 01h	/socgen/trunk/tools/yp/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4314d 19h	/socgen/trunk/tools/yp/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4350d 04h	/socgen/trunk/tools/yp/
117	added yellow pages tools	jt_eaton	4377d 23h	/socgen/trunk/tools/yp/