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[/] [socgen/] [trunk/] [tools/] [yp/] - Rev 134

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Rev	Log message	Author	Age	Path
134	Resynced database socgen now supports elaboration Bad news is that it is now alot slower.	jt_eaton	3307d 11h	/socgen/trunk/tools/yp/
133	Added Desing databases and foundation for elaborations tools	jt_eaton	3350d 12h	/socgen/trunk/tools/yp/
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3382d 09h	/socgen/trunk/tools/yp/
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3486d 03h	/socgen/trunk/tools/yp/
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3941d 09h	/socgen/trunk/tools/yp/
127	final cleanup before DAC	jt_eaton	4056d 05h	/socgen/trunk/tools/yp/
126	added mor1kx cleanup	jt_eaton	4109d 10h	/socgen/trunk/tools/yp/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4154d 04h	/socgen/trunk/tools/yp/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4207d 07h	/socgen/trunk/tools/yp/
122	Moved Nexys2 from opencores.org to digilentinc.com Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components	jt_eaton	4230d 02h	/socgen/trunk/tools/yp/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4250d 08h	/socgen/trunk/tools/yp/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4268d 08h	/socgen/trunk/tools/yp/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4303d 03h	/socgen/trunk/tools/yp/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4338d 12h	/socgen/trunk/tools/yp/
117	added yellow pages tools	jt_eaton	4366d 07h	/socgen/trunk/tools/yp/

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