OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [yp/] - Rev 135

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
135 resynced with socgen, Release V1.0.0 changed tool lic to apache 2.0 jt_eaton 2801d 09h /socgen/trunk/tools/yp/
134 Resynced database
socgen now supports elaboration
Bad news is that it is now alot slower.
jt_eaton 3311d 10h /socgen/trunk/tools/yp/
133 Added Desing databases and foundation for elaborations tools jt_eaton 3354d 11h /socgen/trunk/tools/yp/
131 Added elaboration databases and tools
Added bus map creation tools
jt_eaton 3386d 08h /socgen/trunk/tools/yp/
130 Dec 2014 major release
trimmed out some IP
replaced perl database with Berkeley
jt_eaton 3490d 01h /socgen/trunk/tools/yp/
128 major cleanup
added toolflows for sim,syn,documentation,linting and verilog
added documentation tools
jt_eaton 3945d 07h /socgen/trunk/tools/yp/
127 final cleanup before DAC jt_eaton 4060d 04h /socgen/trunk/tools/yp/
126 added mor1kx
cleanup
jt_eaton 4113d 09h /socgen/trunk/tools/yp/
125 Added two new 6502 cores in www.6502.org

cleaned up sogen xml files and added module name control
jt_eaton 4158d 02h /socgen/trunk/tools/yp/
124 beta release candidate 1
changed design.xml name
aligned schema with filesystem
jt_eaton 4211d 05h /socgen/trunk/tools/yp/
122 Moved Nexys2 from opencores.org to digilentinc.com
Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components
jt_eaton 4234d 01h /socgen/trunk/tools/yp/
121 cleaned up sims, added autogenerated test bench files
removed mrisc and experimental or1k code
jt_eaton 4254d 07h /socgen/trunk/tools/yp/
120 clean up componentGenerators names and directories
sim + lint now synthesis TestBench
jt_eaton 4272d 07h /socgen/trunk/tools/yp/
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace
jt_eaton 4307d 01h /socgen/trunk/tools/yp/
118 optimized gen_verilog
added padring support
added configuration support
added jtag sims
added accellera candidate bus defs
jt_eaton 4342d 11h /socgen/trunk/tools/yp/
117 added yellow pages tools jt_eaton 4370d 05h /socgen/trunk/tools/yp/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.