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[/] [spdif_interface/] [tags/] [beta_2/] [rtl/] - Rev 47

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Rev Log message Author Age Path
47 Transmitter channel status buffer. gedra 7329d 21h /spdif_interface/tags/beta_2/rtl/
46 Transmitter version register. gedra 7329d 22h /spdif_interface/tags/beta_2/rtl/
45 Transmitter component declarations. gedra 7330d 21h /spdif_interface/tags/beta_2/rtl/
44 Transmitter Wishbone bus cycle decoder. gedra 7330d 21h /spdif_interface/tags/beta_2/rtl/
42 Fixed bug with lock event generation. gedra 7331d 22h /spdif_interface/tags/beta_2/rtl/
39 Bug-fix. gedra 7332d 23h /spdif_interface/tags/beta_2/rtl/
38 Signal renaming and bug fix. gedra 7346d 23h /spdif_interface/tags/beta_2/rtl/
37 Converted to numeric_std and fixed a few bugs. gedra 7348d 01h /spdif_interface/tags/beta_2/rtl/
36 Top level entity for receiver. gedra 7348d 01h /spdif_interface/tags/beta_2/rtl/
31 Added data output. gedra 7349d 20h /spdif_interface/tags/beta_2/rtl/
30 Added Wishbone bus cycle decoder. gedra 7350d 21h /spdif_interface/tags/beta_2/rtl/
29 Wishbone bus cycle decoder. gedra 7350d 21h /spdif_interface/tags/beta_2/rtl/
28 Delint'ed and changed name of architecture. gedra 7355d 06h /spdif_interface/tags/beta_2/rtl/
27 Alternate dual port memory implementation for Altera FPGA's. gedra 7355d 21h /spdif_interface/tags/beta_2/rtl/
26 Fixed a few bugs. gedra 7357d 20h /spdif_interface/tags/beta_2/rtl/
25 Changed status reg. declaration gedra 7357d 20h /spdif_interface/tags/beta_2/rtl/
24 Added channel status decoding. gedra 7357d 20h /spdif_interface/tags/beta_2/rtl/
20 Renamed generic and cleaned some lint's gedra 7360d 21h /spdif_interface/tags/beta_2/rtl/
19 Added frame decoder and sample extractor gedra 7360d 21h /spdif_interface/tags/beta_2/rtl/
18 Frame decoder and sample extractor gedra 7360d 21h /spdif_interface/tags/beta_2/rtl/

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