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[/] [spdif_interface/] [trunk/] [rtl/] [vhdl/] - Rev 49

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Rev Log message Author Age Path
49 Changed write signal for status buffers. gedra 7307d 23h /spdif_interface/trunk/rtl/vhdl/
48 Added new components. gedra 7307d 23h /spdif_interface/trunk/rtl/vhdl/
47 Transmitter channel status buffer. gedra 7307d 23h /spdif_interface/trunk/rtl/vhdl/
46 Transmitter version register. gedra 7307d 23h /spdif_interface/trunk/rtl/vhdl/
45 Transmitter component declarations. gedra 7308d 22h /spdif_interface/trunk/rtl/vhdl/
44 Transmitter Wishbone bus cycle decoder. gedra 7308d 22h /spdif_interface/trunk/rtl/vhdl/
42 Fixed bug with lock event generation. gedra 7310d 00h /spdif_interface/trunk/rtl/vhdl/
39 Bug-fix. gedra 7311d 00h /spdif_interface/trunk/rtl/vhdl/
38 Signal renaming and bug fix. gedra 7325d 00h /spdif_interface/trunk/rtl/vhdl/
37 Converted to numeric_std and fixed a few bugs. gedra 7326d 02h /spdif_interface/trunk/rtl/vhdl/
36 Top level entity for receiver. gedra 7326d 03h /spdif_interface/trunk/rtl/vhdl/
31 Added data output. gedra 7327d 21h /spdif_interface/trunk/rtl/vhdl/
30 Added Wishbone bus cycle decoder. gedra 7328d 23h /spdif_interface/trunk/rtl/vhdl/
29 Wishbone bus cycle decoder. gedra 7328d 23h /spdif_interface/trunk/rtl/vhdl/
28 Delint'ed and changed name of architecture. gedra 7333d 07h /spdif_interface/trunk/rtl/vhdl/
27 Alternate dual port memory implementation for Altera FPGA's. gedra 7333d 22h /spdif_interface/trunk/rtl/vhdl/
26 Fixed a few bugs. gedra 7335d 22h /spdif_interface/trunk/rtl/vhdl/
25 Changed status reg. declaration gedra 7335d 22h /spdif_interface/trunk/rtl/vhdl/
24 Added channel status decoding. gedra 7335d 22h /spdif_interface/trunk/rtl/vhdl/
20 Renamed generic and cleaned some lint's gedra 7338d 23h /spdif_interface/trunk/rtl/vhdl/

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