URL https://opencores.org/ocsvn/spdif_interface/spdif_interface/trunk

Subversion Repositories spdif_interface

[/] [spdif_interface/] [trunk/] [rtl/] [vhdl/] - Rev 68

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Rev	Log message	Author	Age	Path
68	evt_hsbf and evt_lsbf signals stayed high too long	gedra	7082d 05h	/spdif_interface/trunk/rtl/vhdl/
62	Cleaned up synthesis warnings.	gedra	7332d 02h	/spdif_interface/trunk/rtl/vhdl/
59	SPDIF transmitter top level.	gedra	7333d 02h	/spdif_interface/trunk/rtl/vhdl/
58	Fixed bug.	gedra	7333d 02h	/spdif_interface/trunk/rtl/vhdl/
57	Added component.	gedra	7333d 02h	/spdif_interface/trunk/rtl/vhdl/
56	Transmitter SPDIF encoder.	gedra	7333d 02h	/spdif_interface/trunk/rtl/vhdl/
53	Fixed bug.	gedra	7335d 02h	/spdif_interface/trunk/rtl/vhdl/
52	Changed address of channel status buffers.	gedra	7335d 02h	/spdif_interface/trunk/rtl/vhdl/
49	Changed write signal for status buffers.	gedra	7338d 01h	/spdif_interface/trunk/rtl/vhdl/
48	Added new components.	gedra	7338d 01h	/spdif_interface/trunk/rtl/vhdl/
47	Transmitter channel status buffer.	gedra	7338d 01h	/spdif_interface/trunk/rtl/vhdl/
46	Transmitter version register.	gedra	7338d 02h	/spdif_interface/trunk/rtl/vhdl/
45	Transmitter component declarations.	gedra	7339d 01h	/spdif_interface/trunk/rtl/vhdl/
44	Transmitter Wishbone bus cycle decoder.	gedra	7339d 01h	/spdif_interface/trunk/rtl/vhdl/
42	Fixed bug with lock event generation.	gedra	7340d 02h	/spdif_interface/trunk/rtl/vhdl/
39	Bug-fix.	gedra	7341d 03h	/spdif_interface/trunk/rtl/vhdl/
38	Signal renaming and bug fix.	gedra	7355d 03h	/spdif_interface/trunk/rtl/vhdl/
37	Converted to numeric_std and fixed a few bugs.	gedra	7356d 05h	/spdif_interface/trunk/rtl/vhdl/
36	Top level entity for receiver.	gedra	7356d 05h	/spdif_interface/trunk/rtl/vhdl/
31	Added data output.	gedra	7358d 00h	/spdif_interface/trunk/rtl/vhdl/

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Subversion Repositories spdif_interface

[/] [spdif_interface/] [trunk/] [rtl/] [vhdl/] - Rev 68

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