URL https://opencores.org/ocsvn/spi/spi/trunk

Subversion Repositories spi

[/] [spi/] [tags/] [rel_5/] [rtl/] [verilog/] - Rev 27

Rev	Log message	Author	Age	Path
27	New directory structure.	root	5570d 11h	/spi/tags/rel_5/rtl/verilog/
18	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7646d 06h	/spi/tags/rel_5/rtl/verilog/
17	Define mess fixed.	simons	7646d 06h	/spi/tags/rel_5/rtl/verilog/
15	Defines set in order.	simons	7646d 10h	/spi/tags/rel_5/rtl/verilog/
13	8-bit WB access enabled.	simons	7647d 03h	/spi/tags/rel_5/rtl/verilog/
10	Slave select signal generation bug fixed, default case added when reading registers, to avoid latches.	simons	7685d 10h	/spi/tags/rel_5/rtl/verilog/
9	Support for 128 bits character length added. Zero value divider bug fixed.	simons	7726d 04h	/spi/tags/rel_5/rtl/verilog/
8	Automatic slave select signal generation added.	simons	7746d 05h	/spi/tags/rel_5/rtl/verilog/
7	Support for 64 bit caharacter len added.	simons	7834d 17h	/spi/tags/rel_5/rtl/verilog/
2	Initial import	simons	8033d 05h	/spi/tags/rel_5/rtl/verilog/