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[/] [spi/] [tags/] [rel_8/] [bench/] [verilog/] - Rev 27

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Rev Log message Author Age Path
27 New directory structure. root 5578d 07h /spi/tags/rel_8/bench/verilog/
26 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7398d 23h /spi/tags/rel_8/bench/verilog/
25 CTRL register bit fields changed, VATS testing support added. simons 7398d 23h /spi/tags/rel_8/bench/verilog/
12 Error fixed. simons 7675d 06h /spi/tags/rel_8/bench/verilog/
9 Support for 128 bits character length added. Zero value divider bug fixed. simons 7733d 23h /spi/tags/rel_8/bench/verilog/
8 Automatic slave select signal generation added. simons 7754d 00h /spi/tags/rel_8/bench/verilog/
7 Support for 64 bit caharacter len added. simons 7842d 13h /spi/tags/rel_8/bench/verilog/
2 Initial import simons 8041d 01h /spi/tags/rel_8/bench/verilog/

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