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[/] [srdydrdy_lib/] - Rev 10

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Rev Log message Author Age Path
10 Fixed "locked" variable in rrslow ghutchis 5265d 13h /srdydrdy_lib/
9 Added rx_gigmac, additional debug work on concentrator & fib ghutchis 5265d 13h /srdydrdy_lib/
8 Added compiling version of bridge example ghutchis 5267d 01h /srdydrdy_lib/
7 Added rrslow ghutchis 5269d 05h /srdydrdy_lib/
6 Modified "B" output buffer for full-rate operation ghutchis 5271d 13h /srdydrdy_lib/
5 Added new component for port ring ghutchis 5272d 05h /srdydrdy_lib/
4 Added example directory with basic bridge ghutchis 5273d 00h /srdydrdy_lib/
3 Added small/synchronizer FIFO, along with minimal testbench ghutchis 5273d 23h /srdydrdy_lib/
2 Initial commit of directory structure and basic components ghutchis 5278d 09h /srdydrdy_lib/
1 The project and the structure was created root 5286d 00h /srdydrdy_lib/

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