URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [env/] [verilog/] - Rev 19

Rev	Log message	Author	Age	Path
19	Fixed several minor bugs in scoreboard, adjusted usage width in sd_fifo_b, and updated component documentation.	ghutchis	5301d 11h	/srdydrdy_lib/trunk/env/verilog/
18	Added scoreboard and scoreboard testbench	ghutchis	5301d 15h	/srdydrdy_lib/trunk/env/verilog/
14	- Modified large FIFO to remove "full" signal and store only N-1 words - changed small FIFO to use memory instance instead of registers - changed sequence generator to enable more complex tests - changed sd_mirror to use combinatorial assign output	ghutchis	5304d 10h	/srdydrdy_lib/trunk/env/verilog/
6	Modified "B" output buffer for full-rate operation	ghutchis	5316d 00h	/srdydrdy_lib/trunk/env/verilog/
3	Added small/synchronizer FIFO, along with minimal testbench	ghutchis	5318d 09h	/srdydrdy_lib/trunk/env/verilog/